This application is based upon and claims the benefit of Japanese Patent Applications No. 2000-211503 filed on Jul. 12, 2000, and No. 2001-185485 filed on Jun. 19, 2001, the contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device having a power semiconductor element such as a MOSFET or an IGBT.
2. Description of the Related Art
A power semiconductor device formed with a power semiconductor element such as a MOSFET or an IGBT and a poly-Si Zener diode is conventionally known. FIGS. 4A to 4C show a method in a stepwise manner for manufacturing a semiconductor device formed with a vertical power MOSFET and a poly-Si Zener diode, which is explained below.
[Step Shown in FIG. 4A]
First, a wafer 51 composed of an n+ type substrate 52 and an nxe2x88x92 type epi-layer (epitaxial layer) 53 disposed on the n+ type substrate 52 is prepared. Then, a p type deep base region 54 is formed in the nxe2x88x92 type epi-layer 53 in an area where the vertical power MOSFET is to be formed (MOSFET formation area) by a photolithography step. Next, a LOCOS film 55 is formed by LOCOS oxidation in an area where the poly-Si Zener diode is to be formed (diode formation area), and then, a gate oxide film 56 is formed by gate oxidation in the MOSFET formation area.
After that, a poly-Si layer is deposited on an entire surface of the wafer 51, and phosphorous (P) is ion-implanted to lower the resistance of the poly-Si layer. The poly-Si layer is patterned, thereby forming gate electrodes 57 in the MOSFET formation area. Further, thermal oxidation is performed to cover the gate electrodes 57 with an oxide film 58. Another poly-Si layer 59 is deposited, and is patterned to remain in the diode formation area. Thermal oxidation is then performed to cover the poly-Si layer 59 with an oxide film 60.
Successively, a p type base region (channel-well region) 61 is formed in the nxe2x88x92 type epi-layer 53 between the adjacent two gate electrodes 57, by a photolithography step. After a specific region is covered with photoresist 62, a p+ type contact region 63 is formed in a surface portion of the p type deep base region 54 and simultaneously a p+ type region 59a are formed in the poly-Si layer 59 by ion-implanting boron (B).
[Step Shown in FIG. 4B]
After the photoresist 62 is removed and a specific region is covered with photoresist 64, arsenic (As) is ion-implanted to form n+ type source regions 65 and to form an n+ type region 59b in the poly-Si layer 59.
[Step Shown in FIG. 4C]
After the photoresist 64 is removed, rounding oxidation is performed by a heat treatment. Accordingly, an oxide film 66 is formed almost on the entire surface of the wafer 51. At that time, accelerated oxidation occurs on the surface of the n+ type regions, so that the thickness of the oxide film 66 on the n+ type regions becomes thicker than that on the p+ type region.
After that, although it is not shown, after contact holes are formed in the oxide film 66, an Al-Si layer is deposited as a wiring layer, and is patterned. Further, the surface of the wafer 51 is covered with a protective film. Thus, the semiconductor device having the vertical power MOSFET and the Zener diode is completed. The method as described above is, however, required being simplified further.
An object of the present invention is to simplify a method for manufacturing a semiconductor device having a power semiconductor element and a diode.
To achieve the above object, according to the present invention, first, an insulation film is formed on a semiconductor layer of a first conductivity type and first and second electrode materials are disposed on the insulation film, respectively in a first area for forming a power semiconductor element and in a second area for forming a diode. A channel-well region of a second conductivity type is formed in a surface portion of the semiconductor layer in the first area, and a first conductivity type impurity is ion-implanted into a surface portion of the channel-well region to form a source (emitter) region of the first conductivity type, into the first electrode material to form a gate electrode, and into a part of the second electrode material to form a first conductivity type region. Then, a heat treatment is performed to form an oxide film by surface oxidation on the first area having the gate electrode and the source (emitter) region, and on the second electrode material including the first conductivity type region. After that, a second conductivity type impurity is ion-implanted into the channel-well region to form a contact region in the first area, and into the second electrode material to form a second conductivity type region in the second area, through the oxide film serving as a mask.
Thus, when the oxide film is formed after ion-implanting the first conductivity type impurity, accelerated oxidation occurs where the first conductivity type impurity is implanted. Therefore, the oxide film can work as a mask for ion-implanting the second conductivity type impurity to form the contact region and the second conductivity type region by utilizing a difference in thickness thereof produced by the accelerated oxidation. As a result, the method for manufacturing the semiconductor device having both the power semiconductor element and the diode can be simplified.